The present invention relates to information processing systems including multiple processing devices linked to multiple memory cards of a main storage memory through a shared interface, and more particularly to means for executing processor initiated diagnostic functions in the memory, while minimizing traffic on the interface.
In recent years, the performance of information processing devices has improved considerably, particularly in terms of more rapid processing of data. Information processing networks increasingly employ multiple processing devices sharing a common interface for transmitting data between the processors and main storage, which typically is composed of multiple memory cards. The current trend is toward larger main storage memories, employing greater numbers of such memory cards. Improvements in memory subsystems have not kept pace with improvements in processors. This is particularly evident when multiple, parallel processors are used in the network. Accordingly, system or network architectures have been modified to compensate for main storage memories which operate relatively slowly as compared to the processing devices. Cache memories and other techniques have been employed, in an attempt to uncouple the processors from the memory cards in main storage.
Whenever a computer system is powered on, the system is not immediately ready for use, but rather is subject to final preparation known as initial program load (IPL). This procedure involves installing initial programs into the system, as well as final testing of the system, including diagnostic testing of the memory arrays in main storage. The arrays are composed of individual memory locations or cells, each cell capable of storing a bit representing either a logical one or a logical zero. The diagnostic testing is intended to confirm that the cells are each capable of accurately storing logical ones and logical zeros, and that no pair of cells are shorted together.
In information processing networks utilizing multiple processors, and multiple memory cards comprising the main storage memory, the traditional approach to the memory diagnostic test is to utilize one or more of the processors to generate a predetermined data pattern and a data store command identifying a particular section of the memory arrays, and to provide these to main storage via the interface. The data pattern is written into the selected section of the memory arrays, and is later read back into the processor through a fetch command issued by the processor. The fetched data is compared to the original pattern to verify proper functioning of that section of the memory arrays.
Of course, all of the memory arrays must be tested, which consumes considerable time on the main storage interface and requires substantial processor overhead. In fact, memory diagnostic tests typically consume from ninety to ninety-five percent of IPL hardware test time. While this problem arises in part from the number of separate data patterns required to verify memory integrity, the principle factor is the processor and interface overhead involved in gaining access to the memory. This difficulty increases with the number of memory cards forming main storage, since a processor performing the tests must access the memory cards sequentially, without any overlap.
Among recent improvements in memory testing techniques are self testing memory devices. For example, U.S. Pat. No. 4,667,330 (Kumagai) discloses a self diagnostic circuit formed on the same chip as the memory arrays, for detecting defective cells. Data to be stored into the arrays also is provided to the self diagnostic circuit followed by a reading of the data out of the arrays, and a comparison with data in the diagnostic circuit In U.S. Pat. No. 4,757,503 (Hayes et. al.) a test generator, formed on a random access memory integrated circuit, produces a predetermined test pattern sequence applied to each of at least two storage arrays in the RAM. Data in each column of one of the storage arrays is compared with data in the equivalent column of the other storage array, with an error signal generated in case of any disagreement.
U.S. Pat. No. 4,782,486 (Lipcon et. al.) discloses a self testing memory in which test patterns are written simultaneously to all memory banks, by a central processing unit through a commonly shared memory control logic. Then, in connection with each memory board, the contents of a reference memory bank is compared with the contents of corresponding locations in the remaining memory banks.
While these approaches have proved satisfactory under certain conditions, they fail to address the need for rapid diagnostic testing of multiple memory cards in a network in which such memory cards interact with multiple processors through a shared interface. Moreover, they require either comparison of different arrays with one another, or logic on each chip, the cost of which can be prohibitive for multiple-chip memory cards.
Therefore, it is an object of the present invention to provide an information processing network in which a processing device can, through a shared interface, initiate overlapping or simultaneous diagnostic tests in multiple memory cards.
Another object of the invention is to reduce the time for manufacturing testing and initial program load testing of memory arrays, by reducing the number of times a processor (or a card tester) must gain access to the arrays in the course of such testing.
Yet another object is to provide an information processing network in which processor initiated diagnostic testing of memory arrays proceeds without delay or interruption due to traffic on the memory interface or asynchronous memory refresh operations.